synplicity教程

资料大小: 5172

所需积分: 0

下载次数:

用户评论: 0条评论,查看

上传日期: 2006-03-27

上 传 者: 发烧友他上传的所有资料

资料介绍

标签:Synplicity(4)教程(157)

synplicity教程:ObjecTIve: becoming familiar with basic features of Synplify using the Synplify GUI
After compleTIng this lab, the user will be able to:
• Build a  project: include all the HDL source files for the design, select the target
architecture and opTIons, compile, and synthesize the design.
• Understand the log file: become familiar with the various secTIons and useful information reported in the log file.
• Use HDL analyst: analyze the HDL source code, inspect the RTL and the mapped schematics, and cross-probe between RTL & technology schematics and the source code.
Build a project, add & compile the HDL source files, and synthesize the design
1. Invoke Synplify
2. Create a new project a. File -> New -> Project File
Or click on the quick access button “P”
3. Add HDL source files
 a. Source -> Add Source Files
  Or click on the quick access button “ADD”
b. Go to synplify_labs\lab1\verilog or vhdl
c. Select alu.v (alu.vhd) and Hdl_demo.v (Hdl_demo.vhd) & click on open
Note:  Make sure that HDL_demo.v/HDL_demo.vhd (top level) is the last file in the list since Synplify picks the last module as the top level module for VERIOG/VHDL designs.
4. Select the target architecture and options
a. Target  -> Set Device Options
Select the following options in the Set Device Options pop-up window:
Technology: Actel 42MX
Part:  42MX09
Speed Grade: Std
Fanout Guide: 16
Note: Your choices are displayed under the “Target ” area in Synplify’s project window.

用户评论

查看全部 条评论

发表评论请先 , 还没有账号?免费注册

发表评论

用户评论
技术交流、我要发言! 发表评论可获取积分! 请遵守相关规定。
上传电子资料
综合在线 日韩欧美 中文字幕_综合在线 日韩欧美 中文字幕精品视频 <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <蜘蛛词>| <文本链> <文本链> <文本链> <文本链> <文本链> <文本链>